Semiconductor equipment 100 having a plurality of semiconductor devices and upper and lower layer wirings according to a prior art is disclosed in Japanese Unexamined Patent Application Publication No. H07-263665. As shown in FIG. 16, the semiconductor equipment 100 includes a plurality of laterally diffused metal oxide semiconductor (i.e., L-DMOS) transistors 101 having a source region S and a drain region D. The L-DMOS transistors 101 are arranged to have a mesh structure. The first wiring layer as the lower layer wiring is formed on the source and drain regions S, D through the first interlayer insulation film. Further, the second wiring layer as the upper layer wiring is formed on the source and drain regions S, D through the second interlayer insulation film.
The lower layer wiring is composed of a plurality of the first source wirings 1 connecting to a plurality of the source regions S and a plurality of the first drain wirings 2 connecting to a plurality of the drain regions D. The upper layer wiring is composed of the second source wiring 3 and the second drain wiring 4. The second source wiring 3 connects to a plurality of first source wirings 1, and the second drain wiring 4 connects to a plurality of first drain wirings 2. The second source wiring 3 and the second drain wiring 4 almost equally divide the semiconductor equipment 100, and have a triangle shape. The second source wiring 3 and the second drain wiring 4 are bonded to a wire 8 by a wire bonding method and the like.
In the semiconductor equipment 100, the second source wiring 3 and the second drain wiring 4 disposed on the L-DMOS transistors 101 are directly bonded. Therefore, it is no need to form a pad region on a semiconductor substrate for bonding, so that an occupation area of the semiconductor equipment 100 is reduced, i.e., a chip size of the semiconductor equipment 100 is reduced.
The L-DMOS transistor 101 in the semiconductor equipment 100 has a cross-sectional structure shown in FIG. 17. FIG. 17 is an enlarged cross-sectional view showing the L-DMOS transistor 101. In the L-DMOS transistor 101, the first source wiring 1 and the first drain wiring 2 are arranged alternately. Therefore, the surfaces of both an insulation film such as the second interlayer insulation film 7 and a metal film such as the second drain wiring 4 have a large concavity and convexity. In a bonding process for bonding the wire 8, a crack 9 may arise in the second interlayer insulation film 7 disposed under the wire 8. Specifically, the crack 9 arises from a convexity and concavity portion 90 between the insulation film and the metal film. Therefore, the L-DMOS transistor 101 may short or leak current by the crack 9, so that the L-DMOS transistor 101 fails to operate. Further, the concavity and the convexity generated by both a LOCOS region 5 and a gate electrode 14 arise on the surface structure of the substrate. Therefore, a bonding strength between the wire 8 and the second drain wiring 4 becomes weak, so that the wire 8 may fails to bond to the second drain wiring 4.